Delay-locked loops (DLLs) are sometimes used in the delaying of a particular signal of arbitrary wave shape by a fraction of the period of another signal. FIG. 1 (Prior Art) is a diagram of a conventional delay-locked loop 1 usable for this purpose. The particular signal of arbitrary wave shape is signal SIN. The delayed version of SIN is signal SOUT. The other signal is the signal CLKIN. In operation, the signal CLKIN is passed through a variable delay line 2. The delay of delay line 2 is controlled to be equal to one period of the signal CLKIN. The signal CLKOUT that is output from the delay line is fed back to a second input of a phase detector 3. The signal CLKIN is supplied to a first input of phase detector 3. Phase detector 3 adjusts the delay of delay line 2 via the signal CONTROL1 such that the phase of an edge of the CLKOUT signal matches the phase of an edge of the signal CLKIN.
FIG. 2 (Prior Art) is a diagram that illustrates operation of DLL 1. The upper waveform illustrates the signal CLKIN. The rising edges of CLKIN are labeled A, B, C and D as illustrated. The next three waveforms down in the diagram represent three versions of CLKIN that are delayed by different amounts of time by delay line 2. The second waveform illustrates a situation in which delay line 2 delays CLKIN a lesser amount, the next waveform down illustrates a situation in which delay line 2 delays CLKIN a larger amount, and the third waveform down illustrates a situation in which delay line 2 delays CLKIN a still larger amount. The rising edge A in these three waveforms is the delayed version of the rising edge A of CLKIN shown in the top waveform. Note that in the waveform labeled CLKOUT (LOCKED) that first edge A of the delayed signal is phase-aligned with the second edge B of CLKIN. DLL 1 can lock in this condition and adjust the delay of delay line 2 such that this phase relationship between CLKOUT and edge B of CLKIN is maintained. In this lock condition, the delay through the delay line is one period of CLKIN.
In the example of FIG. 1, the value of control signal CONTROL1 that controls delay line 2 is known, as is the relationship of the delay of delay line 2 to the various possible values of CONTROL1. Accordingly, a mathematical operation can be performed on the value of CONTROL1 such that values of control signals CONTROL2 can control an identical delay line 4 (identical to delay line 2) such that the delay through delay line 4 is a desired fraction or percentage of the delay through delay line 2. The mathematical operation is represented in FIG. 1 by block 5. For example, if the signal SOUT is to be a delayed version of SIN where the delay is to be one half of the period of the period of CLKIN, then value CONTROL1 may be divided by two and the divided value may be used as CONTROL2 to control delay line 4.
The bottom three waveforms of FIG. 2 represent an undesirable condition that can sometimes occur, depending on the operation and design of the DLL. This condition is referred to here as “aliasing” or a “false lock”. Rather than the delay through delay line 2 being one period of CLKIN, the delay through delay line 2 is two periods of CLKIN. Note that edge A of delayed signal CLKOUT in the bottom three waveforms is about two periods later than the corresponding edge A of the undelayed signal CLKIN in the upper waveform. The delayed edge A of CLKOUT aligns in time with the third rising edge C of signal CLKIN, rather than the second rising edge B of signal CLKIN. DLL 1 can lock in this condition. If block 5 operates in the same manner as in the non-aliased locking condition, then SOUT will be delayed with respect to SIN by the wrong amount of time. New circuits and techniques for preventing aliasing and false lock problems are sought.